PCASM.TXT 07-JUL-2003
------------------------------ 8088 INSTRUCTIONS -------------------------------
ADD ADC AND CMP OR SBB SUB TEST XOR
r,r r,m m,r r,i m,i flags: o s z a p c
DEC INC r m flags: o s z a p
NEG r m flags: o s z a p c
NOT r m flags: none
DIV IDIV MUL IMUL I = signed, flags: mostly
ax(q):dx(r) <- dx:ax / (r16 or m16) dx:ax <- ax * (r16 or m16) garbage
al(q):ah(r) <- ah:al / (r8 or m8) ax <- al * (r8 or m8)
CBW CWD flags: none
ax <- extend sign al dx:ax <- extend sign ax
SHL SHR (SAL) SAR r,1 m,1 r,cl m,cl flags: o s z a p c
ROL ROR RCL RCR r,1 m,1 r,cl m,cl flags: o c
MOV r,r r,m m,r r,i m,i flags: none
r16,sr sr,r16 m16,sr sr,m16 (no m,m no sr,sr no sr,i)
XCHG r,r r,m eXCHanGe flags: none
LDS LES r16,m16 (sr,m16+2) Load far pointer, flags: none
LEA r16,m Load Effective Address flags: none
PUSH POP r16 m16 sr PUSH: [--sp] <- r16 flags: none
PUSHF POPF flags: 0 n io_pl o d i t s z 0 a 0 p 1 c
(p = 1 = even parity)
LAHF SAHF Load/Store low 8 bits of Flags to/fr AH
JMP short(8) near(16) far(16:16) or indirect near (r16 or m16) far (m16:m16)
Jcond JCXZ range: -128 +127 bytes; most aliases not shown
JB JAE JBE JA JE JNE JL JGE JLE JG JS JNS JC JNC JO JNO JP JNP
LOOP LOOPE LOOPNE LOOP = DEC CX + JNE and flags unaffected
CALL RET RETF RET i RETF i call near or far or indirect near or far
i = (even) number of bytes to pop
INT i8 INTO IRET software interrupt flags: i t
CLC STC CMC CLear, SeT, and CoMplement flags:
CLD STD Carry, Direction, and Interrupt
CLI STI
IN a,i8 a,dx OUT i8,a dx,a flags: none
REP MOVS STOS LODS REPE REPNE CMPS SCAS flags: vary
es:[di++] <- ds:[si++] cx-- Byte or Word (++ assumes d flag = 0)
AAA AAS AAM AAD DAA DAS bcd opcodes flags: vary
NOP XLAT ESC HLT LOCK WAIT misc opcodes flags: none
GENERAL PURPOSE REGISTERS:
AX AH:AL optimized for: ADD imm, MOV mem, TEST imm, XCHG, etc.
used by: MUL, DIV, CBW, CWD, IN, OUT, LAHF, LODS, AAA, etc.
BX BH:BL data index; used by XLAT
CX CH:CL used by: LOOP, REP, JCXZ; CL is used by shifts & rotates
DX DH:DL used by: MUL, DIV, CWD, IN and OUT
SI data index; REP source index
DI data index; REP destination index
BP base pointer; stack segment index
SP stack pointer; used by: PUSH, POP, CALL, RET, INT and IRET
SEGMENT REGISTERS:
CS code segment
DS data segment
SS stack segment
ES extra segment
EFFECTIVE ADDRESS (EA) CLOCKS SEGMENT
[disp16] 6 (= DS unless shown)
[BX] 5
[SI] 5
[DI] 5
[BX+SI] 7
[BX+DI] 8
[BP+SI] 8 SS
[BP+DI] 7 SS
[BP+disp8/16] 9 SS
[BX+disp8/16] 9
[SI+disp8/16] 9
[DI+disp8/16] 9
[BX+SI+disp8/16] 11
[BX+DI+disp8/16] 12
[BP+SI+disp8/16] 12 SS
[BP+DI+disp8/16] 11 SS
segment override 2 segment
LEGEND:
r = general purpose register (both 8 and 16 bits unless specified)
m = memory location (EA) (both 8 and 16 bits unless specified)
i = immediate value (constant) (both 8 and 16 bits unless specified)
a = accumulator register (al or ax)
sr = segment register (always 16 bits)
disp = displacement for address
FOR 80386:
r = general purpose register (both 16 and 32 bits unless specified)
m = memory location (EA) (both 16 and 32 bits unless specified)
i = immediate value (constant) (8, 16 and 32 bits unless specified)
The letters B, W and D are appended to a mnemonic to specify the size of the
operand if it is not determined by a register size (e.g: al, si or ecx) or by
the default size (USE16/32). For example: MOVSW, SCASB, LOOPD, LOOPW, PUSHW i.
------------------------------ 80386 EXTENSIONS --------------------------------
IMUL r,r r,m r,i r,r,i r,m,i flags: o c
Shifts and rotates allow immediate counts other than just 1 (modulo 32)
SHLD SHRD r,r,i8 m,r,i8 r,r,cl m,r,cl flags: o s z a p c
CWDE CDQ flags: none
eax <- extend sign ax edx:eax <- extend sign eax
MOVSX MOVZX r,r8 r,m8 r32,r16 r32,m16 flags: none
MOV r32,control control,r32 r32,debug debug,r32 flags: garbage
LFS LGS LSS r,m (sr,m+2) load far pointer flags: none
POPA PUSHA PUSH i flags: none
Jcond range increased to: -32768 +32767 (use "short" for -128 +127)
SETcond r8 m8 flags: none
SETB SETAE SETBE SETA SETE SETNE SETL SETGE SETLE SETG SETS SETNS
SETC SETNC SETO SETNO SETP SETNP most aliases not shown
INS es:[edi++] <- [dx] OUTS [dx] <- ds:[esi++] flags: none
Byte, Word or Double (++ assumes d flag = 0)
ENTER i16,i8 LEAVE create/terminate stack frame flags: none
BOUND r,m:m check array bounds flags: none
BSF BSR r,r r,m Bit Scan Forward/Reverse flags: z
BT BTR BTS BTC Bit Test (and Reset, Set or Complement)
r,i8 m,i8 r,r m,r
ARPL r16,r16 r16,m16 Adj Requested Privilege Level flags: z
CLTS CLear Task Switched flag flags: none
LAR LSL r,r r,m Load Access Rights / Seg Limit, flags: z
LGDT SGDT LIDT SIDT m48 Load/Store Descriptor Table, flags: none
LLDT SLDT r16 m16 (Global, Interrupt, Local)
LMSW SMSW r16 m16 Load/Store Machine Stat Word flags: none
LTR STR r16 m16 Load/Store Task Register flags: none
VERR VERW r16 m16 VERify selector for Read/Write flags: z
ADDITIONAL SEGMENT REGISTERS (SELECTORS):
FS extra segment
GS extra segment
32-BIT ADDRESS MODES:
--- disp32 --- [index*scale+disp32]
[EAX] [EAX+disp8/32] [EAX+index*scale] [EAX+index*scale+disp8/32]
[EBX] [EBX+disp8/32] [EBX+index*scale] [EBX+index*scale+disp8/32]
[ECX] [ECX+disp8/32] [ECX+index*scale] [ECX+index*scale+disp8/32]
[EDX] [EDX+disp8/32] [EDX+index*scale] [EDX+index*scale+disp8/32]
[ESI] [ESI+disp8/32] [ESI+index*scale] [ESI+index*scale+disp8/32]
[EDI] [EDI+disp8/32] [EDI+index*scale] [EDI+index*scale+disp8/32]
--- [EBP+disp8/32] --- [EBP+index*scale+disp8/32]
--- --- [ESP+index*scale] [ESP+index*scale+disp8/32]
index = any except ESP (or none) scale = 1, 2, 4 or 8
---------------------------- MATH COPROCESSOR (FPU) ----------------------------
FLD FSTP m32 m64 m80 st(i) LoaD/STore (push/Pop) FPU stack
FST m32 m64 st(i) STore without popping
FILD FISTP m16 m32 m64 LoaD/STore & convert Integer/real
FIST m16 m32 STore without popping
FBLD FBSTP m80 LoaD/STore & convert BCD/real
FLD1 FLDZ FLDPI FLDL2E FLDL2T FLDLG2 FLDLN2 LoaD (push) constant
1.0 0.0 pi ln2(e) ln2(10) log(2) ln(2)
FXCH st(i) eXCHange st and st(i)
FADD FSUB FSUBR FMUL FDIV FDIVR ( FADD = FADDP st(1),st )
st,st(i) st(i),st m32 m64
FADDP FSUBP FSUBRP FMULP FDIVP FDIVRP
st(i),st
FIADD FISUB FISUBR FIMUL FIDIV FIDIVR
m16 m32
F2XM1 FABS FCHS FSIN FCOS FRNDINT FSQRT st <- function st
2^x-1 abs neg sin cos round sqrt
2 inputs 1 output (like FADD): FPATAN
2 outputs 1 input: FPTAN FSINCOS
2 inputs 2 outputs: FSCALE
FYL2X FYL2XP1 st <- st(1) * ln2(st)
FPREM FPREM1
FXTRACT
FCOM FCOMP FCOMPP FICOM FICOMP
FUCOM FUCOMP FUCOMPP
FTST
FCLEX FNCLEX
FDECSTP FINCSTP
FFREE
FINIT FNINIT
FLDCW FSTCW FNSTCW
FLDENV FSTENV FNSTENV
FNOP
FRSTOR FSAVE FNSAVE
FSTSW FNSTSW
FXAM
FDISI FNDISI FENI FNENI
FSETPM
LEGEND:
st = st(0) = top of FPU stack consisting of eight 80-bit registers
st(i) = ith item relative to st, e.g: st(1) = next on stack
-Loren Blaney